Many of today's solid-state shift register circuits use multilevel emitter-coupled logic circuits to achieve high speed operation while limiting power dissipation. Some of these shift registers incorporate set and clear functions within the emitter-coupled logic circuitry. To achieve right-left shift and synchronous and asynchronous parallel loading has generally required the use of multiple separate logic gates which decrease speed and increase power dissipation and the area of silicon necessary to implement the shift register and the gates.
The publication entitled "A Low-Power, Bipolar, Two's Complement Serial Pipeline Multiplier Chip" by Jack Kane, IEEE Journal of Solid-State Circuits, Vol. SC-11, No. 5, October 1976, pages 669-678, illustrates a D-type master-slave flip-flop which illustrates a combination of EFL and emitter-coupled stages. This configuration has relatively high speed and only moderate power dissipation. Multicontrol shift registers using this type of flip-flop are not known.
It is desirable to have a multicontrol solid-state shift register circuit which utilizes EFL and has relatively high speed operation, modest power dissipation, and can be implemented in a relatively modest area of silicon.